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| M08035, m08045 data sheet v1 macom ? october 2014 080x5-dsh-001 M08035/m08045 sd, hd, 3g multi-rate reclocker applications ? surveillance/cctv cameras ? industrial and professional cameras ? digital video recorders (dvr) ? video mixers and switchers ? digital image transmitter devices ? distribution amplifiers ? repeaters the M08035/m08045 are serial digital video reclockers with integrated trace equalization and automatic rate detect (ard) circuitry. the M08035 operates at data rates of 270 mbps an d 1485 mbps, while the m08045 operates at data rates of 270 mbps, 1485 mbps, and 2970 mbps. the M08035/m08045 have an input jitter tolerance (ijt) of greater than 0.6 unit intervals (ui) and can provide retimed serial outputs with very low output jitt er. the reclocker requires a single, external, 27 mhz crystal, which is used as the reference clock. it includes per lane input equalization for up to 40" of fr 4 trace and two connectors in addition to output de-emphasis. these devices feature integrated supply regul ators, allowing them to be powered from 1.2 v, 1.8 v, 2.5 v, or 3.3 v supply voltages. when operating at 1.2 v, they consume only 230 mw at 3g and hd. furthermore, the power rails for the core, input, and output circuitry are electrically independent and as such ma y be connected to different voltage rails on the board. this feature enables the M08035/m08045 to be dc coupled to any upst ream or downstream device regardless of its input/output voltage level. these devices may be configured by setting the internal regist ers though standard two-wire and four-wire interfaces. limited configuration is also possible through hardware pin settings. the M08035/m08045 are offered in green and rohs compliant, 6 mm x 6 mm, 40-pin qfn packages. M08035/m08045 block diagram ie ie ie ie sdoan sdoap sdob/sclkon sdob/sclkop 4:1 mux reclocker sdi0n sdi0p sdi1n sdi1p sdi2n sdi2p sdi3n sdi3p 50 ? buffer w/ de 50 ? buffer w/ de features ? greater than 0.6 ui input jitter tolerance ? integrated 50 input termination ? input equalization and output de-emphasis for 40" of fr4 trace ? 230 mw power consumption (1.2 v operation) ? integrated regulators for multi-vo ltage operation (1.2 v - 3.3 v) ? electrically independent input , output, and core supply rails ? output enable/disable and configurable auto or manual bypass mode ? automatic and manual modes for rate indication and selection ? loss of lock (lol), loss of signal (los) and data rate indication ? two-wire and four-wire seria l interface programmability ? industrial operating temperature range (-40 c to +85 c) ? optional recovered serial clock output
M08035, m08045 data sheet v1 macom ? 2 080x5-dsh-001 ordering information part number package operating temperature M08035g-11* 6x6 mm, 40-pin qfn package -40 c to 85 c m08045g-11* 6x6 mm, 40-pin qfn package -40 c to 85 c revision history revision level date description v2 release october 2014 updated mode_sel, sdob/sclk_en, xreg _en description in table 3-1 . a (v1) release may 2011 initial release. M08035/m08045 marking diagram part number lot num ber date and country code xxxx .x yyww cc m08045 g-11 xxxx .x yyww cc M08035 g-11 M08035, m08045 data sheet v1 macom ? 3 080x5-dsh-001 1.0 electrical characteristics unless noted otherwise, specifications apply for typical recommended operating conditions shown in ta bl e 1-2 , with dv ddo = 1.2 v, av ddcore = 1.2 v, dv ddcore = 1.2 v, av ddi = 1.2 v, pcml inputs/outputs at 800 mv ppd (r load = 50 ) , and prbs 2 10 ? 1 test pattern at 2.97 gbps. table 1-1. absolute maximum ratings symbol parameter note minimum maximum unit av ddi analog supply for input circuitry 1, 3 -0.5 3.6 v av ddo analog supply for output circuitry 1, 3 -0.5 3.6 v dv ddio digital supply for input/output circuitry 1, 3 -0.5 3.6 v dv ddcore digital core positive supply 1, 3 -0.5 1.5 v av ddcore analog core positive supply 1, 3 -0.5 1.5 v t store storage temperature 1, 3 -65 150 c v max, io maximum/minimum input/output voltage on any input/output pin 1, 3 -0.5 av ddi +0.5 v v esd, hbm human body model (hbm) 1, 2, 3 -2 2 kv v esd, cdm charge device model (cdm) 1, 2, 3 -500 500 v lu latch up @ 85 c 1, 3 -150 150 ma notes: 1. exposure of the device beyond the minimum/maximum limits may cause permanent damage. limits listed in the above table are str ess limits only, and do not imply functiona l operation within these limits. 2. hbm and cdm per jedec class 2 (jesd22-a114-b). 3. limits listed in the above table ar e stress limits only and do not imply func tional operation within these limits. electrical characteristics M08035, m08045 data sheet v1 macom ? 4 080x5-dsh-001 table 1-2. recommended operating conditions symbol parameter minimum typical maximum unit dv ddio digital i/o positive supply 1.14 1.2, 1.8, 2.5, or 3.3 3.47 v av ddi analog input positive supply 1.14 1.2, 1.8, 2.5, or 3.3 3.47 v av ddo analog output positive supply 1.14 1.2, 1.8, 2.5, or 3.3 3.47 v av ddcore analog core positive supply 1.14 1.2 1.26 v dv ddcore digital core positive supply 1.14 1.2 1.26 v t case case temperature -40 25 +85 c table 1-3. power consumption specifications symbol parameter conditions note typical maximum unit p total total power consumption av ddi = av ddo =dv ddio =dv ddcore = av ddcore = 1.2 v sdo swing level 1 1, 3 230 290 mw 1, 4 250 350 p total total power consumption av ddi = av ddo =dv ddio =dv ddcore = av ddcore = 1.2 v sdo swing level 2 1, 3 240 300 mw 1, 4 260 360 p total total power consumption dv ddcore = av ddcore = 1.2 v av ddi = dv ddio = 1.2 v av ddo = 1.8 v sdo swing level 3 1, 3 260 370 mw 1, 4 270 450 dv ddcore = av ddcore = 1.2 v av ddi = dv ddio = 3.3 v av ddo = 3.3 v sdo swing level 3 2, 3 720 1070 ja junction to ambient thermal resistance 5 35 ? c/w jc junction to case thermal resistance 5 3 ? c/w note: 1. internal regulators disabled. 2. internal regulators enabled. 3. sdob/sclk disabled. 4. sdob/sclk enabled. 5. airflow = 0 m/s. electrical characteristics M08035, m08045 data sheet v1 macom ? 5 080x5-dsh-001 table 1-4. high speed input electrical specifications symbol parameter conditions note minimum typical maximum unit dr input data rate (m0803 5) sd operation ? 270 ? mbps hd operation ? 1485, 1483.5 ? mbps reclocker bypassed 18 ? 3400 mbps dr input data rate (m0804 5) sd operation ? 270 ? mbps hd operation ? 1485, 1483.5 ? mbps 3g operation ? 2970, 2967 ? mbps reclocker bypassed 18 ? 3400 mbps v in differential input voltage at the chip input (point blank) input equalization disabled los enabled (default setting) 1, 3 300 800 1600 mv ppd v icm input common mode voltage at the chip input (point blank) input equalization disabled los enabled av ddi -0.6 ? av ddi +0.1 v r in input termination to av ddi 40 50 60 ie input equalization 2 ? 0, 2, 4, 6 ? db i in maximum high-speed input current 4 -100 100 ma note: 1. for example, 1200 mv ppd = 600 mv pp for each single-ended terminal. 2. these values correspond to: off, small, me dium, and large respectively. the small set ting is not available in hardware mode. 3. when using long traces and input equalization enabled, macom recommends a minimum input swing of 400 mv ppd . with video stress patterns, dc coupling produces the best results. 4. exposure of the device beyond the minimum/maximum limits may cause permanent damage. limits listed in the above table are str ess limits only, and do not imply functiona l operation within these limits. electrical characteristics M08035, m08045 data sheet v1 macom ? 6 080x5-dsh-001 table 1-5. high speed output electrical specifications symbol parameter conditions note minimum typical maximum unit dr output data rate (M08035) sd operation ? 270 ? mbps hd operation ? 1485, 1483.5 ? reclocker bypassed 18 ? 3400 dr output data rate (m08045) sd operation ? 270 ? mbps hd operation ? 1485, 1483.5 ? 3g operation ? 2970, 2967 ? reclocker bypassed 18 ? 3400 f clock serial clock output frequency (M08035) sd operation 1, 7 ? 270 ? mhz hd operation ? 1485, 1483.5 ? f clock serial clock output frequency (m08045) sd operation 1, 7 ? 270 ? mhz hd operation ? 1485, 1483.5 ? 3g operation ? 2970, 2967 ? v out differential output swing (peak to peak, differential) swing level 1 2 470 600 720 mv ppd swing level 2 2 600 800 970 swing level 3 2,3 960 1200 1500 v ocm output common mode voltage dc coupled 2, 6 ? av ddo -v out /4 ? t r /t f sdo output rise/fall time from 20%-80% of the swing for all levels ? 85 130 ps t r /t f rise/fall time mismatch from 20%-80% of the swing for all levels 6? ? 30ps dcd data output duty cycle distortion for all data rates 4 ? ? 15 ps r out output termination to av ddo 40 50 60 de output de-emphasis 5 ? 0, 2, 4, 6 ? db note: 1. serial clock output enabled. 2. differential swing is maximum output level (de-emphasis is di sabled or max level when de-emphasis is enabled), max level incl udes overshoot. 3. 1200 mv ppd requires av ddo to be 1.8 v or higher. 4. measured in reclocked mode. 5. these values correspond to: off, small, me dium, and large respectively. the small set ting is not available in hardware mode. 6. guaranteed by design. 7. see section 4.7 for information on clock data alignment. electrical characteristics M08035, m08045 data sheet v1 macom ? 7 080x5-dsh-001 table 1-6. digital input/output electrical characteristics symbol parameter note minimum maximum unit v oh output logic high 1 0.80 x dv ddio ?v v ol output logic low 2 ? 0.2 x dv ddio v v ih input logic high ? 0.85 x dv ddio dv ddio + 0.5 v v if input logic floating ? 0.25 x dv ddio 0.75 x dv ddio v v il input logic low ? 0 0.15 x dv ddio v note: 1. i oh = -3 ma 2. i ol = 3 ma table 1-7. reclocker specifications (M08035) symbol parameter conditions note minimum typical maximum unit t lock lock time (asynchronous) automatic rate detection enabled 1 ? ? 6 ms f lbw, peak loop bandwidth peaking 1 ? 0.1 ? db f lbw loop bandwidth (nominal setting) hd operation (1.485 gbps) 1 ? 0.85 ? mhz sd operation (270 mbps) 1 ? 0.17 ? j tol input jitter tolerance hd, and sd operation 2 > 0.6 ? ? ui p-p j gen total output jitter hd operation (1.485 gbps) 2, 3 ? 0.04 0.06 ui p-p sd operation (270 mbps) 2, 3 ? 0.02 0.05 note: 1. 0.2 ui input jitter applied at sdi input. 2. measured with prbs2 10 -1. 3. input jitter = 20 ps p-p. electrical characteristics M08035, m08045 data sheet v1 macom ? 8 080x5-dsh-001 table 1-8. reclocker specifications (m08045) symbol parameter conditions note minimum typical maximum unit t lock lock time (asynchronous) automatic rate detection enabled 1 ? ? 6 ms f lbw, peak loop bandwidth peaking 1 ? 0.1 ? db f lbw loop bandwidth (nominal setting) 3g operation (2.97 gbps) 1 ? 1.7 ? mhz hd operation (1.485 gbps) 1 ? 0.85 ? sd operation (270 mbps) 1 ? 0.17 ? j tol input jitter tolerance 3g, hd, and sd operation 2 > 0.6 ? ? ui p-p j gen total output jitter 3g operation (2.97 gbps) 2, 3 ? 0.07 0.11 ui p-p hd operation (1.485 gbps) 2, 3 ? 0.04 0.06 sd operation (270 mbps) 2, 3 ? 0.02 0.05 note: 1. 0.2 ui input jitter applied at sdi input. 2. measured with prbs2 10 -1. 3. input jitter = 20 ps p-p. table 1-9. xtalp/n and reference clock electrical specifications symbol parameter note minimum typical maximum unit f ref xtal/ref clock frequency 3 ? 27 ? mhz f ref, ppm xtal/ref clock frequency accuracy ? -100 0 100 ppm c load xtal load capacitance 1 ? 20 ? pf clock jitt jitter (rms) 2, 4 ? ? 1 ps clock dct reference clock duty cycle tolerance 240 ? 60% r in input impedance 2, 5 200 750 1500 v in input amplitude 2 0.8 ? 1.2 v t r /t f rise/fall time 2, 6 ? 2 6 ns note: 1. this capacitance is supplied internally (no external cap is required). 2. when using an external reference clock source, this should be ac coupled through a 0.1 f capacitor. 3. when using an external clock a small increase in jitter may be seen. for best performance a crystal is recommended. 4. jitter bandwidth is from 12 khz to 20 mhz. 5. measured with tdr module. 6. 10% to 90% rise and fall times. M08035, m08045 data sheet v1 macom ? 9 080x5-dsh-001 2.0 typical performance characteristics figure 2-1. M08035 eye diagram at reclocker input prbs15 @ 1.485 gbps figure 2-2. M08035 eye diagram at reclocker output prbs15 @ 1.485 gbps figure 2-3. m08045 eye diagram at reclocker input prbs15 @ 3 gbps figure 2-4. m08045 eye diagram at reclocker output prbs15 @ 3 gbps M08035, m08045 data sheet v1 macom ? 10 080x5-dsh-001 3.0 pinout diagram, pin description, and package drawing figure 3-1. M08035/m08045 pinout diagram xtaln/refclk 30 xtalp 29 mf5 28 27 26 25 24 av ddcore 22 sdi3n 21 sdi3p 23 av ddi mf4 av ddi mf0 1 mf1 2 mf2 3 mf3 4 5 6 7 sdi0n 9 av ddcore 10 sdi0p 8 av ddi mode_sel n/c av dd i 11 sdi1p 12 sdi1n 13 av ddcore 14 15 16 xreg_en 17 19 20 18 av ddi sdi2p sdi2n av ddco re dv ddcore 40 dv ddio 39 38 sdoap 37 sdoan 36 av ddo 35 sd/xhd 34 33 sdob/sclkp 32 sdob/sclkn 31 xalarm dv dd cor e M08035/m08045 6mmx6mm qfn center ground pad sdob/clk_en av dd cor e pinout diagram, pin description, and package drawing M08035, m08045 data sheet v1 macom ? 11 080x5-dsh-001 table 3-1. M08035/m08045 pin description (1 of 2) pin name pin number(s) type description av ddcore 5, 14, 16, 20, 26 power analog positive supply av ddi 8, 11, 17, 21, 23 power analog positive supply av ddo 35 power analog positive supply dv ddcore 31, 40 power digital core positive supply dv ddio 39 power digital core positive supply avss center ground pad power ground sdi0p, sdi0n 6, 7 pcml input data input lane0; true/complement sdi1p, sdi1n 12, 13 pcml input data input lane1; true/complement sdi2p, sdi2n 18, 19 pcml input data input lane2; true/complement sdi3p, sdi3n 24, 25 pcml input data input lane3; true/complement sdoap, sdoan 37, 36 pcml output data output lane a; true/complement sdobp/sclkp, sdobn/sclkn 34, 33 pcml output data output lane b; true/complement xtalp 29 reference clock 27 mhz reference xtal connection xtaln/refclk 30 reference clock 27 mhz reference xtal connection or 27 mhz reference clock input mode_sel 9 cmos input sets the devi ce control/configuration mode: l = device is in register access mode with two-wire serial control (sic2) f = device is in hardware control mode (hardware mode) h = device is in register access mode with four-wire serial control (sic4) sdob/sclk_en 27 cmos input sdob/sclk output enable: l = sdob/sclk output disabled f = serial data output enabled h = serial clock output enabled xreg_en 15 cmos input regulator enable control, as in figure 3-6 , but pull up resistor is to av ddi . l = integrated regulators enabled f = integrated regulators disabled sd/xhd 38 cmos output cmos sd/xhd rate indicator: l = hd/3g data rate h = sd rate xalarm 32 output (open drain) alarm indicator for all channels (logical or of all individual channel alarms). termination - open l = alarm asserted h = normal operation serial control mode (two-wire/four-wire): xalarm in interrupt mode hardware mode: not supported pinout diagram, pin description, and package drawing M08035, m08045 data sheet v1 macom ? 12 080x5-dsh-001 mf0 1 cmos input four-wire serial contro l mode: serial clock input (sclk) two-wire serial control mode: clock input from master host (scl) hardware mode: unused mf1 2 cmos input four-wire serial cont rol mode: serial data output (so) two-wire serial control mode: serial data i/o (sda) hardware mode: unused mf2 3 cmos input four-wire serial control mode: serial data in (si) two-wire serial control mode: address bit 0 (add0) hardware mode: input trace equalization control for all sdi inputs (ie_ctrl) h = large input eq f = medium input eq l = input eq disabled mf3 4 cmos input four-wire serial contro l mode: active low chip select (xcs) two-wire serial control mode: address bit 1 (add1) hardware mode: output de-emphasis (d e) control for sdo outputs (de_ctrl) h = large output de f = medium output de l = de disabled mf4 22 cmos input four-wire serial control mode: not used. tie to dv ddio or leave floating two-wire serial control mode: address bit 2 (add2) hardware mode: reclocker bypass control (rc_bypass) l/f = normal operation, reclocker not bypassed h = reclocker bypassed mf5 28 cmos input four-wire serial control mode: not used. tie to avss or leave floating two-wire serial control mode: address bit 3 (add3) hardware mode: sdo disable control for all outputs (sdo_dis) h = sdo disabled output logic high l/f = sdo enabled nc 10 reserved do not connect table 3-1. M08035/m08045 pin description (2 of 2) pin name pin number(s) type description pinout diagram, pin description, and package drawing M08035, m08045 data sheet v1 macom ? 13 080x5-dsh-001 figure 3-2. i-analog figure 3-3. o-analog sdip av dd i av ss sdin av dd i av ss 50 ? 50 ? input buffer with trace equalizer av ss av dd o 50 ? sdon av dd o 50 ? av ss av ss sdop pinout diagram, pin description, and package drawing M08035, m08045 data sheet v1 macom ? 14 080x5-dsh-001 figure 3-4. ref clock figure 3-5. i-digital with no pull-up av dd i 20pf xtaln/refclk av dd i 20pf refclk av dd core 500 k ? input av ss 2.0k ? dv dd io pinout diagram, pin description, and package drawing M08035, m08045 data sheet v1 macom ? 15 080x5-dsh-001 figure 3-6. i-digital with pull-up figure 3-7. i-digital with pull-down input av ss 2.0k ? 100 k ? dv dd io input av ss 2.0k ? 100k ? dv dd io pinout diagram, pin description, and package drawing M08035, m08045 data sheet v1 macom ? 16 080x5-dsh-001 figure 3-8. 3-state/i-digital figure 3-9. o-digital av ss input av ss 2.0k ? vref_high av ss vref_low 100 k ? 100k ? av ss dv dd io dv dd io dv dd io dv dd io av ss output dv dd io pinout diagram, pin description, and package drawing M08035, m08045 data sheet v1 macom ? 17 080x5-dsh-001 the M08035/m08045 are assembled in 40-pin, 6 mm x 6 mm quad flat no-lead (qfn) packages. the exposed die paddle serves as the ic ground (av ss ), and the primary means of thermal dissipation. this die paddle should be soldered to the pcb. a cross-section of the qfn package is shown below. figure 3-10. o-open drain figure 3-11. qfn package cross section av ss output dv dd io pinout diagram, pin description, and package drawing M08035, m08045 data sheet v1 macom ? 18 080x5-dsh-001 figure 3-12. package outline drawing (amkor) 0.60 dia. d1/2 d1 d/2 d e1/2 e/2 e1 e 2x a 2x 0.10 b c a n seating plane 0.05 b c 0.10 2x c 0.10 0.10 2x b a1 a c c c a a3 a2 0 0.10 c 3 2 1 terminal tip e/2 e (l) (datum a or b) nx r see exposed pad variation see exposed pad variation max. 0.50 0.30 pitch variation d y symbols exposed pad variations pinout diagram, pin description, and package drawing M08035, m08045 data sheet v1 macom ? 19 080x5-dsh-001 figure 3-13. package outline drawing (ase) M08035, m08045 data sheet v1 macom ? 20 080x5-dsh-001 4.0 functional description 4.1 functional block diagram figure 4-1 illustrates the M08035/ m08045 block diagram. the s ubsequent sections provide additional detail on the operation of the devices. figure 4-1. M08035/m08045 block diagram sdi0 p sdi0n sdi1 p sdi1n sdi 2p sdi2 n sdi 3p sdi3 n 4x1 mux reclocker 50 ? outpu t b uf fer programm able de-emphas is sdoap sdoan sdob/ sclkp sdob/ sclkn regulator analog supply av dd _core dv dd _core av dd i crystal oscillator xtaln/refclk xtal p control logic i 2 c/spi serial bus and hardware mode sd/xhd mf[0:5] mode_sel xreg_en av dd o dv dd io regulator digital supply 50 ? inp ut buffer programmable equalization sdob/s clk_ en sdob /clke n xalarm functional description M08035, m08045 data sheet v1 macom ? 21 080x5-dsh-001 4.2 high-speed differential inputs the M08035/m08 045 feature four di fferential inputs compat ible with pcml. lvds and lvpecl signal levels are also accommodated. serial data to be retimed is presented to these four inputs. each input is terminated with a 50 termination to av ddi . av ddi can be supplied from any voltage ranging from 1.2 v to 3.3 v. in order to improve signal integrity when used in large systems, ea ch input also comes equipped with programmable input equalization (ie) for fr4 trace. there are four settings for input equalization: 0 db (or no equalization), 2 db, 4 db, and 6 db. in serial control mode, the input equalization level for each input may be set by programming the desired value to reg00h-reg03h. alternatively, in hardware mode, the input equalization for all of the inputs may be set globally through the ie_ctrl (mf2 ) pin. in hardware mode only the three settings of 0 db, 4 db, and 6 db are available. in most video applications, it is important to avoid ac coupled data interfaces between devices wherever possible. in addition to reducing the number of components, dc coup ling will result in more system jitter margin. in order to accommodate dc coupling with the upstream device, the av ddi power domain of the M08035/m08045 is electrically independent from all other power domains, allowing it to be tied to the v dd of the upstream device. this is demonstrated in figure 4-2 below. alternatively and under certain conditions, the M08035/m08045 allow for the inputs to be self biased eliminating the need for an electrical connection between the supply voltages of the upstream device and the M08035/ m08045. this configuration offers the benefit of keeping the supply of the previous device and the power domain(s) of the M08035/m08045 completely isolated, while using dc coupling. ac coupling should not be used with the self bias interface. this self biasing scheme is demonstrated in figure 4-3 below. when using the M08035/m08045 in self biased mode, specific conditions must be met: 1. the self biased inputs must be dc coupled. no ac coupling is supported in self biased mode. 2. the av ddo of the upstream device must be 2.5 v or greater. av ddo levels 1.2 v and 1.8 v are not supported in this mode. 3. the common mode of the upstream signals must be greater than 600 mv. 4. internal voltage regulators are disabled. 5. all inputs are configured in self biased mode. combinat ion of self biased and non-self biased is not supported. figure 4-2. M08035/m08045 av ddi connected to the v dd of the upstream device upstream device M08035/m08045 av 1.2v ? 3.3v vdd 50 ddi 50 functional description M08035, m08045 data sheet v1 macom ? 22 080x5-dsh-001 a loss of signal (los) detector monitors each input and issues an alarm when the input signal level dips below the detection threshold set in register 06h. see section 4.3 for more information on the los circuit. in order to correct any duty cycle distortion (dcd) in the input signal, or any dc offset buildup in the internal signal path, a dc correction loop has been a dded. programming register 0dh bit 1 to a '1' will disable the dc correction loop for all inputs. the M08035/m08045 include a 4:1 multiplexer. this allows any one of the four input signals to be routed to the reclocker. by default sdi0 is selected to be routed to sdo0. the selected input can be set using mux control register 07h. by default, only the selected input is powered up, with all other inputs powered down. when an input is powered down, its associated los circuitry is disabled. if required, all the other inputs can also be powered up by setting bit[3] in register 0dh. this will allow a fa ster response if rapid input switching is required as there is no delay waiting for the circuitry to power-up and adjust to the input signal, but has the disadvantage of consuming more power. with all inputs enabled, the power consumption increases by 100 mw. 4.3 los (loss of signal) the M08035/m08045 have integrated los circuits on each of their four high-speed inputs. this circuit monitors the input amplitude and if it falls below the detection threshold it asserts the los alarm bit by setting this to a logic high. these alarm bits are latched and will need to be reset with the clr_alarms , register 85h, by setting bit 0 to a high and back to a low. hysteresis is built into the lo s circuit to avoid chattering. the los threshold can be set to a different level by using the bits[7:5] in register 06h, this changes the level on all four inputs. by default, the los alarm mutes the signa l from that particu lar input. setting register 06h bit[3] to a high will disable this feature. figure 4-3. self biasing the input of M08035/m08045 upstream device M08035 /m08045 av ddi do not supply a voltage 2.5v? 3.3v av ddo 50 50 dc coupled only, do not use internal voltage regulator 0.1 f per av ddi pin note: 1. for self bias applications, no vo ltage must be applied to the av ddi pin. every av ddi pin should be decoupled to gnd with a 0.1 f capacitor as shown in figure 4-3 . functional description M08035, m08045 data sheet v1 macom ? 23 080x5-dsh-001 4.4 high-speed output description there are two high-speed outputs available on the M08035/m08045. by default, only sdoa is powered up, setting bit 2 of register 0ch high will enable sdob. the output signal will be a copy of sdoa. in hardware mode, sdob is enabled with the sdob/sclk_en input pin in a floating (f) or high (h) (see ta bl e 3-1 ). a further function of this output is a serial clock source. by setting register 06h, bit 0 to high, the reclockers recovered clock is output to the sdob/sclk pins. in hardware mode this function is selected by setting sdob/ sclk_en high (see ta b l e 3-1 ). the M08035/m08045 feature differential current mode logic (cml) drivers with integrated 50 pull ups to av ddo for the output of each reclocker channel. av ddo may be supplied from any voltage ranging from 1.2 v to 3.3 v. the differential, peak-to-peak, output swing for each cml driver is programmable and may be set to 600 mv ppd , 800 mv ppd , or 1200 mv ppd . please note that the 1200 mv ppd output swing setting is only available when av ddo is supplied from a voltage of 1.8 v or greater. the swing setting may be programmed by writing to register 09h for sdoa, and register 0bh for sdob. in order to improve signal integrity when used in large systems, each output also comes equipped with programmable de-emphasis (de) for fr4 trace. there are four settings for output de-emphasis: 0 db (or no de), 2 db, 4 db, and 6 db. in serial control mode, the output de-emphasis level for each input may be set by programming the desired value to register 09h for sdoa and register 0ah for sdob. alternatively, in hardware mode, the de-emphasis level for all of the outputs may be globally set through pin de_ctrl (mf3). in hardware mode only the three settings of 0 db, 4 db, and 6 db are available. in most video applications, it is important to avoid ac coupled data interfaces between devices wherever possible. in addition to reducing the number of components, dc coup ling will result in more system jitter margin. in order to accommodate dc coupling with the upstream device, the av ddo power domain of the M08035/m08045 is electrically independent from all other power domains therefore allowing it to be tied to the v dd of the downstream device. this is demonstrated in figure 4-4 below. if ac coupling is desired or necessary, then the capacitor should be at least 10 f. figure 4-4. M08035/m08045 av ddo connected to the v dd of the downstream device downstream device M08035/m08045 vdd 1.2v ? 3.3v av ddo 50 50 functional description M08035, m08045 data sheet v1 macom ? 24 080x5-dsh-001 4.5 logic signals to allow interfacing to logi c levels other than the 1.2 v core voltage, or any of the analog input and output supplies, the digital interface signals are referenced to dv ddio which is an isolated power domain. dv ddio may be supplied from any voltage ranging from 1.2 v to 3.3 v. many digital control pins have three states, high (h), low (l), or floating (f). in order to assert the f or floating state, the pin must be left unconnected or undriven. 4.6 control modes the M08035/m08045 may be configured in four separate control modes. the control mode is determined by the setting of the mode_sel pin as shown in ta bl e 4-1 below. the mic mode is a subset of the two-wire interface mode and is initiated by writing to special reserved address when the device is set in two-wire interface mode. table 4-1. control mode setting mode_sel control mode mode_sel = f hardware control mode (hic) mode_sel = h four-wire serial interface control mode (sic4 or spi) mode_sel = l two-wire serial interface control mode (sic2 or i 2 c) memory interface configuration mode (mic) when the reclocker is configured through an external eeprom functional description M08035, m08045 data sheet v1 macom ? 25 080x5-dsh-001 4.6.1 hic mode configuring the M08035/m08045 in hardware mode avoids the complication of adding a microcontroller, but offers limited control options. when in hardware mode, the mf (multi function io) pins are configured as shown in ta bl e 4-2 below. 4.6.2 four-wire interface mode (sic4) in this mode, a four-wire serial interface is used to progra m the device's internal registers, configuring the operation of the M08035/m08045. when in sic4 mode, mf[0:3] pins comprise the four-wire bus as shown in ta bl e 4-3 below. the interface shifts data in from the external controller on the rising edge of sclk. the serial i/o operation is gated by xcs. data is shifted in to the M08035/m08045 from the host (master) to si on the falling edge of sclk, and shifted out through so on the rising edge of sclk. to address a register, a 10-bit input needs to be shifted, consisting of the first bit (start bit, sb = 1), the second bit (operation bit, op = 1 for read, = 0 for write), and the 8- bit address (msb first). table 4-2. mf pin configuration in hardware mode mf hic mode pin name function mf2 ie_ctrl input trace equalization control for all sdi inputs h = 6 db input eq f = 2 db input eq l = 0 db input eq mf3 de_ctrl output de-emphasis (de) control for all sdo outputs h = 6 db of output de f = 4 db of output de l = 0 db output de mf4 rc_bypass reclockers bypass control for all outputs l/h = normal operation, reclocker not bypassed h = reclocker bypassed mf5 sdo_dis sdo disable control for all outputs h = sdo disabled output logic high l/f = sdo enabled note: in this mode, xalarm is not supported. table 4-3. mf pin configuration in four-wire interface mode mf sic4 mode pin name function mf0 sclk serial clock input mf1 so serial data output mf2 si serial data input mf3 xcs chip select (active low) functional description M08035, m08045 data sheet v1 macom ? 26 080x5-dsh-001 figure 4-6 illustrates a serial write mode followed by a serial read mode. to initiate a write sequence, xcs goes low before the falling edge of sclk. on ea ch falling edge of the clock, the 18 bi ts consisting of the sb = 1, op = 0, addr, and data, are latched into the input shift register through si. the rising edge of xcs may occur before or after the falling edge of sclk for the last bit. upon re ceipt of the last bit, one additi onal cycle of sclk is necessary before data transfers from the input shift register to the addressed register. to initiate a read sequence, xcs go es low before the falling edge of sclk. on each falling edge of sclk, the 10 bits consisting of sb = 1, op = 1, and the 8-bit addr are wr itten to the serial input shift register and copied to the serial output shift register. on the next rising edge after the address lsb, the sb and 8 bits of the data are shifted out. the sb for a read is always 1. the 4-wire interface supports multiple consecutive writes. in this case, the address header is not needed and each additional 8 bits of data will be wri tten into consecutive addresses. if co nsecutive read/write cycles are being performed, it is not necessa ry to insert an extra clock cycle between read/write cycles, however one extra clock cycle is needed after the last data bit of the last read/write cycle. figure 4-5. four-wire interface word format figure 4-6. four-wire write followed by a read sequence sclk xcs 1 si so 2 3 ... 10 11 ... 17 18 19 20 address[7:0] data[7:0] w 21 22 23 ... 31 tcs tdh tds 1 r 1 address[7:0] 32 d7 dx d1 d0 33 ... 41 tcs tch tcs trdd functional description M08035, m08045 data sheet v1 macom ? 27 080x5-dsh-001 on a write cycle, any bits that follow the expected number of bits are ignored, and only the first 15 bits following sb and op are used. on a read cycle, any extra clock cycles will re sult in the repeat of the data lsb. an invalid sb or op renders the operation undefined. the falling edge of xcs always resets the serial operation for a new read or write cycle. detailed timing inform ation is shown below. figure 4-7. four-wire sequential write table 4-4. four-wire interface timing timing symbol description min max unit tds data set-up time 5 ? ns tdh data hold time 5 ? ns tcs xcs set-up time 5 ? ns tch xcs hold time 5 ? ns tfreq, write four-wire interface write clock frequency ? 40 mhz tfreq, read four-wire interface clock read frequency, dv ddio =2.5 v or 3.3 v ?40mhz four-wire interface read clock frequency, dv ddio =1.8 v ? 20 mhz four-wire interface read clock frequency, dv ddio =1.2 v ? 5 mhz t duty sclk duty cycle 40 60 % tdd read data output delay (measured with max 30 pf loading, dv ddio =3.3 v) 18ns sclk xcs 1 si so 2 3 ... 11 12 13 14 ... 20 21 address[7:0] 1 st data[7:0] r/w 22 23 ... 29 30 2 nd data[7:0] 3 rd data[7:0] tcs tdh tds 1 ... functional description M08035, m08045 data sheet v1 macom ? 28 080x5-dsh-001 4.6.3 two-wire interface mode (sic2) in this mode a two-wire serial interface is used to program the device's internal registers, configuring the operation of the M08035/m08045. when in sic2 mode, mf[0:5] pins are configured as shown below. each device has an individual address and is addressed us ing an address byte, which is latched upon power-on- reset (por). in this mode, the M08035/m08045 are i 2 c-compatible slave devices that can operate at 100 khz and 400 khz for all allowed voltages seen at the dv ddio pin. the M08035/m08045 allow for forty different addresses to be programmed using the inputs add[3:0]; these inputs have three states, low (l), high (h) and floating (f). the slave addresses are from 21h to 48h. table 4-5. mf pin configuration in two-wire interface mode mf sic4 mode pin name function mf0 scl clock input from master host mf1 sda serial data input/output mf2 add0 address bit 0 mf3 add1 address bit 1 mf4 add2 address bit 2 mf5 add3 address bit 3 table 4-6. M08035/m08045 2-wire interface address map (1 of 2) dec add hex add bin add pin setting function add3 add2 add1 add0 32 20 010 0000b l l l l eeprom only, address 50h 32 20 010 0000b l l l h eeprom only, address 51h 32 20 010 0000b l l h l eeprom only, address 52h 32 20 010 0000b l l h h eeprom only, address 53h 33 21 010 0001b l h l l slave 1 34 22 010 0010b l h l h slave 2 35 23 010 0011b l h l f slave 3 36 24 010 0100 b l h h l slave 4 37 25 010 0101b l h h h slave 5 38 26 010 0110b l h h f slave 6 39 27 010 0111b l h f l slave 7 40 28 010 1000 b l h f h slave 8 41 29 010 1001b l h f f slave 9 42 2a 010 1010b l f l l slave 10 43 2b 010 1011b l f l h slave 11 44 2c 010 1100b l f l f slave 12 45 2d 010 1101b l f h l slave 13 functional description M08035, m08045 data sheet v1 macom ? 29 080x5-dsh-001 46 2e 010 1110b l f h h slave 14 47 2f 010 1111b l f h f slave 15 48 30 011 0000 b l f f l slave 16 49 31 011 0001 b l f f h slave 17 50 32 011 0010 b l f f f slave 18 51 33 011 0011 b f l l l slave 19 52 34 011 0100 b f l l h slave 20 53 35 011 0101 b f l l f slave 21 54 36 011 0110 b f l h l slave 22 55 37 011 0111 b f l h h slave 23 56 38 011 1000 b f l h f slave 24 57 39 011 1001b f l f l slave 25 58 3a 011 1010b f l f h slave 26 59 3b 011 1011b f l f f slave 27 60 3c 011 1100b f h l l slave 28 61 3d 011 1101b f h l h slave 29 62 3e 011 1110b f h l f slave 30 63 3f 011 1111b f h h l slave 31 64 40 100 0000b f h h h slave 32 65 41 100 0001b f h h f slave 33 66 42 100 0010b f h f l slave 34 67 43 100 0011b f h f h slave 35 68 44 100 0100 b f h f f slave 36 69 45 100 0101b f f l l slave 37 70 46 100 0110b f f l h slave 38 71 47 100 0111b f f l f slave 39 72 48 100 1000 b f f h l slave 40 table 4-7. supported at 24c01 eeprom addresses dec add hex add bin add fixed by eeprom address pin setting add6 add5 add4 add3 add2 add1 add0 80 50 010 0000b h l h l l l l 81 51 010 0001b h l h l l l h 82 52 010 0010b h l h l l h l 83 53 010 0011b h l h l l h h table 4-6. M08035/m08045 2-wire interface address map (2 of 2) dec add hex add bin add pin setting function add3 add2 add1 add0 functional description M08035, m08045 data sheet v1 macom ? 30 080x5-dsh-001 figure 4-8 illustrates typical waveforms and timing seen at scl and sda for a re ad and write operation. figure 4-8. two-wire interface timing diagram table 4-8. two-wire interface timing specifications (standard mode or fast mode) symbol parameter minimum typical maximum unit f scl clock frequency, scl ? ? 400 khz t low clock pulse width low 1.3 ? ? s t high clock pulse width high 1 ? ? s t aa clock low to data out valid 0.05 ? 0.9 s t hdsta start hold time 200 ? ? ns t susta start set-up time 200 ? ? ns t hddat data in hold time 0 ? ? ns t sudat data in set-up time 100 ? ? ns t susto stop set-up time 200 ? ? ns t dh data out hold time 50 ? ? ns notes: 500 pf @ 100 khz and 250 pf @ 400 khz with 1k pull-up. functional description M08035, m08045 data sheet v1 macom ? 31 080x5-dsh-001 4.6.4 mic mode operation in this mode, the reclocker is in itialized with an eeprom. to use this mode, the eeprom must be programmed with the register data required. the i 2 c address of the memory can be 50h, 51h, 52h or 53h; the reclocker loads its register contents from this address. this mode is enabled when the i 2 c mode is set and address 20h has been hardwired on the address pins. when the reclocker locates the memory at one of the above addresses, it sets itself into i 2 c quasi-master mode. it will then load its register s from the eeprom. addresses 00h to 19h should be used when only one reclo cker is used. register 0fh contains the number of slave reclockers; if there are none this is set to 0. once the master has finished the task of downloading the re gisters, it will revert to sl ave mode at add ress 20h and can be accessed for debugging purposes. note that when using mic power mode supply, ramp time is important. the eeprom should be powered from the same supply as dv ddio and the ramp up of the supply should be < 100 ms. if the ramp time is not met, the reclocker i 2 c will time-out before the eeprom is ready to receive serial data. the target eeprom is the at24c01 or equivalent. if there is more than one reclocker to be programmed, a checksum is used to confirm that the data is correct. this works as follows: 1. the slave reclocker sums all registers from 00h to 1ah, then truncates this to leave the 8 lsb bits. this is then compared with the value 2eh. if it is not equal, then the registers are not loaded and it returns to the default value. it will then try up to 512 time s before timing out. when the checksum is equal to 2eh, the registers are loaded with the eeprom settings. 2. to make the checksum = 2eh, register 1ah must be programmed with the 8 lsbs from the following calculation: register 1ah = 2eh - (sum of registers 00h to 19h) functional description M08035, m08045 data sheet v1 macom ? 32 080x5-dsh-001 4.7 reclocker operation 4.7.1 clock recovery this block generates a serial clock signal at a frequency close to the data rate. the clock signal is generated by a phased locked loop (pll) which uses the 27 mhz input clock as a reference. the presence of the reference clock is monitored by the de vice. an alarm bit (noref) in register 88h is set to '1' when a suitable reference clock is not present. once the pll has locked to the reference clock, the reflol bit in the same register will be set to '0'. a value of '1' in this bit indicates th at the pll has not locked to the input reference clock. the frequency locked clock signal is supplied to the phase lock block. in this block, a bang-bang phase comparator is used to make fine adjustments to the phase and frequency of the clock, aligning it with the incoming serial data. once the clock signal is phase and frequency aligned with the serial data stream, it is used to re-time the data, producing a clean data signal that is provided at the output of the device. the phase lock block uses an integrated, programmable loop filter. the bandwidth of the phase lock block may be programmed using the bw[2:0] bits in register 16h. a wide bandwidth increases the jitter tolerance and reduces the lock time of the loop. however, a wide bandwidth also allows more jitter from the input serial data stream to be transferred to the output. alternatively, a low bandwidth setting causes the loop to reject more of the incoming data stream's jitter, while increasing lock time, and reducing input jitter tolerance. the bandwidth setting can be optimized for each system. furthermore, since the phase lock block uses a non-linear, bang-bang loop, the bandwidth of the system is inversely proportional to the incoming data stream's jitter. this offers several advantages over linear plls. it achieves higher jitter attenuation with large input jitter, while it corrects for small variations quickly with low input jitter. with higher input jitter, the loop automatically reduces the bandwidth, causing more of the jitter to be rejected. conversely, a data stream with lower jitter will cause the loop bandwidth to be widen ed. note that bandwidth settings greater than 2x will increase output jitter. when the recovered serial clock output is enabled, the clock alignment to the sdoa data output will be typically 60 ps, where the falling edge of the clock la gs the transition edge of the sdoa signal. 4.7.2 automatic rate detection the reclocker features an automatic rate detector (a rd) circuit that monitors the input signal rate and automatically sets the reclocker to the correct video rate. the data rate determined by the ard block may be read from bits 1:0 in register 89h as shown in ta bl e 4-9 . table 4-9. reclocker rate detection reg89h (bits 1:0) function 00b reclocker unlocked 01b sd rate detected 10b hd rate detected 11b 3g rate detected (m08045) functional description M08035, m08045 data sheet v1 macom ? 33 080x5-dsh-001 as an alternative to the ard, the user may manually set the reclocker to the desired data rate by programming bits[3:2] in register 12h to the desired values as shown in ta bl e 4-10 . please note that when configured in manual ard mode, the reclocker is guaranteed to lock to the program data rate. however, it may also lock to the harmonics of that program data rate as well. for example, if the reclocker is programmed to lock to hd data, it will al so try to lock to 3g data as 2.97 gbps is exactly twice 1.485 gbps. when in auto-bypass mode, if the ard cannot determine the rate of the input data stream, it will switch the reclocker into bypass mode. this allows a data rate other than those specified to be passed through the reclocker. the auto-bypass mode may be disabled through register 14h. 4.7.3 lock detection several circuits monitor each reclocker for loss of lock. one in particular compares the recovered serial clock to one derived from the reference clock. if the clock frequency is within 2000 ppm of the serial data frequency, the loss of lock (lol) alarm will be set to '0'. if the clock is outside of this window, then the lol alarm will be asserted to '1'. the lol bit can be read from bit[0] in register 88h. 4.7.4 reference clock the M08035/m08045 can operate from a crystal or an external reference clock, but better jitter results are obtained with a crystal. if using an external reference clock, this should be a 27 mhz clock with a frequency accuracy of 100 ppm or better. reference clock jitter is important and care must be taken to supply a low jitter reference clock to the reclocker of 1 ps rms or less. the reference clock may either be from an exte rnal cmos clock oscillator or an external parallel resonance crystal. if a low jitter 27 mhz signal is already available on the board then it may be used. due to the higher jitter, a genlocked 27 mhz clock is likely not suitable for this device. when supplying an external clock signal, it is recommended to use ac coupling through a 0.1 f capacitor. refer to ta bl e 1-7 for recommended input levels. 4.8 sd/xhd output when the reclocker is locked to the input data, the sd/xhd output indicates whether an sd or hd rate is detected. when a 3g rate is being rece ived, the output will indi cate hd. this output is designed to be connected to the slew rate control on a downstream cable driver. the sd/xhd pin has two available modes as shown in ta b l e 4-11 . these are controlled by the sdalg bit, reg 18h[5], by default this is a 0 and only goes high when the reclocker is locked to a 270 mbps input signal. this mode sets the fast edge on the cable driver and allows for any signal in the reclockers data range to be bypassed. if the slow edge is set, any signal above 540 mbps would be distorted by the slow edge on the cable driver. table 4-10. reclocker data rate selection reg12h (bits 3:2) function 00b ard enabled 01b manual sd rate programmed 10b manual hd rate programmed 11b manual 3g rate programmed (m08045) functional description M08035, m08045 data sheet v1 macom ? 34 080x5-dsh-001 when sdalg is high it also sets the sd/xhd pin high when the reclocker is unlocked. this is used when the user requires other sd rates such as 143 mbps and 360 mbps to be output from the cable driver with the slow sd edge when the reclocker is not locked. 4.9 xalarm the xalarm output pin is provided so the user can monitor alarm activity on the reclocker. the output is open drain as shown in figure 3-10 . ta bl e 4-12 shows the reclocker alarms and their function. the assertion of any of the alarms in ta bl e 4-12 will trigger xalarm. the xalarm pin may be used when the device is controlled using standard four-wire or two-wire serial interfaces (sic4 and sic2). the xalarm pin operates in an interrupt mode. it goes low on the assertion of any of the internal alarm flags and stays low for a fixed period of time before returning to high (see figure 4-9 ). this period is set by the interrupt control register (0eh). by default this is 0 and that corresponds to 20 ns. the maximum period is 2.560 s, when int[3:0] is set to fh. the xalarm pin is designed to be connected to a microprocessor's interrupt pin. after the interrupt occurs, the microprocessor can read the reclocker's alarm registers to determine which alarm was asserted. table 4-11. sd/xhd output algorithm rate (gbps) sd/xhd pin sdalg bit = 0 sdalg bit = 1 0.270 h h 1.485/1.4835 l l 2.97/2.967 l l unlocked l h note: please note that xalarm is not supported in hardware control mode (hic). table 4-12. reclocker alarm function alarm function los asserted when input signal goes below los threshold as set in register 06h. lol asserted when reclocker cannot lock to the incoming data. noref asserted when no input reference is present at the reference clock inputs. reflol asserted when frequency lock block cannot lock to the reference clock input. functional description M08035, m08045 data sheet v1 macom ? 35 080x5-dsh-001 4.9.1 reading register alarm bits the los and lol alarm bits are latched when asserted. after reading they should be cleared using the clralrm bit in register 88h. this bit needs to be set to '1' to reset the alarms. it should then be reset to a '0' to re-enable normal alarm operation. 4.10 internal regulator both digital and analog cores of the M08035/m08045 are designed to run from a 1.2 v supply. if a 1.2 v supply is not available locally, then the internal regulator can be used to create this domain from av ddi /av ddo and dv ddio . setting the xreg_en pin low, enables the internal regulator. this regulator generates a 1.2 v domain at pins av dd and dv dd . see figure 4-10 through figure 4-12 for the three different supply configurations. note that the decoupling capacitors should be at least 100 nf. when the internal regulator is used, all the current for the device is taken through the av ddi /av ddo and dv ddio pins. because of this, care should be taken to ensure that the supplies to these pins are sufficient to handle the total current. figure 4-9. xalarm-output interrupt mode los lol xalarm t interrupt occurs when los or lol changes state. xalarm pulse width is programmable. functional description M08035, m08045 data sheet v1 macom ? 36 080x5-dsh-001 figure 4-10. all power pins connected to 1.2 v, internal regulators not used figure 4-11. av ddi , av ddo , and dv ddio connected to a supply at 1.8 v or 3.3 v, 1.2 v is supplied to av dd and dv dd , internal regulator not used av ddi av ddo dv ddio xreg_en av ddcore dv ddcore 1.2v xreg_en av ddcore dv ddcore 1.8v-3.3v 1.2v av ddi av ddo dv ddio functional description M08035, m08045 data sheet v1 macom ? 37 080x5-dsh-001 note: in order to simplify the diagrams, av ddi , av ddo , and dv ddio are shown to be shorted together. in practice, they may all be separated and connected to different supply domains if desired. av ddo is sensitive to noise and therefore should be filtered through a ferrite bead, with a 10 nf ceramic capacitor adjacent to each av ddo pin. since this core can take a current in the order of 500 ma, the ferrite bead should be very low resistance to ensure the drop across it is minimal. figure 4-12. av ddi , av ddo , and dv ddio connected to a supply at 1.8 v or 3.3 v. internal regulator generates on-chip 1.2 v 1.8v-3.3v av ddi av ddo dv ddio xreg_en av ddcore dv ddcore M08035, m08045 data sheet v1 macom ? 38 080x5-dsh-001 5.0 control registers map and descriptions table 5-1. M08035/m08045 register map (1 of 2) addr register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default r/w input/output configuration 00h input eq config 0 rsvd rsvd ie0[1] ie0[0] rsvd rsvd rsvd rsvd 00h r/w 01h input eq config 1 rsvd rsvd rsvd rsvd ie1[1] ie1[0] rsvd rsvd 00h r/w 02h input eq config 2 rsvd rsvd rsvd rsvd ie2[1] ie2[0] rsvd rsvd 00h r/w 03h input eq config 3 rsvd rsvd rsvd rsvd ie3[1] ie3[0] rsvd rsvd 00h r/w 04h input polarity flip 0 rsvd rsvd pol1 rsvd rsvd pol0 rsvd rsvd 00h r/w 05h input polarity flip 1 rsvd rsvd pol3 rsvd rsvd rsvd pol2 rsvd 00h r/w 06h los config/clk en lvl[2] lvl[1] lvl[0] f_los nvrsq sqpol rsvd sclk_en 20h r/w 07h input mux ctrl rsvd rsvd rsvd rsvd rsvd rsvd in[1] in[0] 40h r/w 08h rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd c8h r/w 09h sdoa ctrl rsvd rsvd rsvd rsvd lvl_a[1] lvl_a[0] de_a[1] de_a[0] 88h r/w 0ah sdob ctrl de rsvd rsvd de_b[1] de_b[0] rsvd rsvd rsvd rsvd 00h r/w 0bh output ctrl rsvd rsvd rsvd sdoa_mute sclk_lvl[1] sclk_lvl[0] rsvd rsvd 08h r/w 0ch sdob ctrl rsvd rsvd rsvd rsvd rsvd sdob_en rsvd rsvd 02h r/w 0dh gbl ctrl1 rsvd rsvd rsvd rsvd forcesdion rsvd offloop pdall 00h r/w 0eh interrupt ctrl rsvd rsvd rsvd rsvd int[3] int[2] int[1] int[0] 00h r/w 0fh micreg rsvd rsvd micdev micdev micdev micdev micdev micdev 00h r/w reclocker configuration 10h rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 30h r/w 11h rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 00h r/w 12h rclk ctrl 0 rsvd rsvd rsvd rsvd rate[1] rate[0] bypass pdown 00h r/w 13h rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 00h r/w 14h rclk ctrl 1 rsvd rsvd rsvd rsvd rsvd rsvd rsvd bypdis 00h r/w 15h rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 00h r/w 16h rclk bw ctrl rsvd bw[2] bw[1] bw[0] rsvd rsvd rsvd rsvd 20h r/w 17h rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd c0h r/w 18h rsvd rsvd rsvd sdalg rsvd rsvd rsvd rsvd rsvd c8h r/w 19h rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 03h r/w control registers map and descriptions M08035, m08045 data sheet v1 macom ? 39 080x5-dsh-001 checksum for memory interface configuration 1ah checksum chksum chksum chksum chksum chksum chksum chksum chksum 55h r/w status/monitoring registers 80h master reset rst rst rst rst rst rst rst rst 00h r/w 81h chip id id[7] id[6] id[5] id[ 4] id[3] id[2] id[1] id[0] 0bh r 82h chip rev rev[7] rev [6] rev [5] rev [4] rev [3] rev [2] rev [1] rev [0] 04h r 83h los status 0 rsvd rsvd los1 rsvd rsvd los0 rsvd rsvd 00h r 84h los status 1 rsvd rsvd los3 rsvd rsvd rsvd los2 rsvd 00h r 85h clear alarms rsvd rsvd rsvd rsvd rsvd rsvd softrst clralarms 00h r/w 87h checksum result chkres chkres chkres ch kres chkres chkres chkres chkres 00h r/w 88h rclk alarms rsvd rsvd noref reflol rsvd rsvd rsvd lol 00h r 89h rclk rate detect rsvd rsvd rsvd rsvd rsvd rsvd rate[1] rate[0] 00h r 96h lol config rsvd mask[0] rsvd rsvd rsvd rsvd rsvd rsvd 00h r/w note: 1. rsvd are reserved bits that should never be changed from the default level. table 5-1. M08035/m08045 register map (2 of 2) addr register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default r/w control registers map and descriptions M08035, m08045 data sheet v1 macom ? 40 080x5-dsh-001 5.1 registers description 5.1.1 input/output configuration register address: 00h default: 00h register name: input eq config 0 description: select input equalization level, input 0 register address: 01h default: 00h register name: input eq config 1 description: select input equalization level, input 1 register address: 02h default: 00h register name: input eq config 2 description: select input equalization level, input 2 bit bit description default r/w 7:6 reserved 00b r/w 5:4 00b: sdi0, input equalization disabled 01b: sdi0, small input equalization level 10b: sdi0, medium input equalization level 11b: sdi0, large input equalization level 00b r/w 3:2 reserved 00b r/w 1:0 reserved 00b r/w bit bit description default r/w 7:6 reserved 00b r/w 5:4 reserved 00b r/w 3:2 00b: sdi1, input equalization disabled 01b: sdi1, small input equalization level 10b: sdi1, medium input equalization level 11b: sdi1, large input equalization level 00b r/w 1:0 reserved 00b r/w bit bit description default r/w 7:6 reserved 00b r/w 5:4 reserved 00b r/w 3:2 00b: sdi2, input equalization disabled 01b: sdi2, small input equalization level 10b: sdi2, medium input equalization level 11b: sdi2, large input equalization level 00b r/w 1:0 reserved 00b r/w control registers map and descriptions M08035, m08045 data sheet v1 macom ? 41 080x5-dsh-001 register address: 03h default: 00h register name: input eq config 3 description: select input equalization level, input 3 register address: 04h default: 00h register name: input polarity flip 0 description: setting to a '1' inverts associated input, inputs 0 to 1 register address: 05h default: 00h register name: input polarity flip 1 description: setting to a '1' inverts associated input, inputs 2 to 3 bit bit description default r/w 7:6 reserved 00b r/w 5:4 reserved 00b r/w 3:2 00b: sdi3, input equalization disabled 01b: sdi3, small input equalization level 10b: sdi3, medium in put equalization level 11b: sdi3, large input equalization level 00b r/w 1:0 reserved 00b r/w bit bit description default r/w 7 reserved 0b r/w 6 reserved 0b r/w 5 0b: sdi1, input normal 1b: sdi1, input inverted 0b r/w 4 reserved 0b r/w 3 reserved 0b r/w 2 0b: sdi0, input normal 1b: sdi0, input inverted 0b r/w 1 reserved 0b r/w 0 reserved 0b r/w bit bit description default r/w 7 reserved 0b r/w 6 reserved 0b r/w 5 0b: sdi3, input normal 1b: sdi3, input inverted 0b r/w 4 reserved 0b r/w 3 reserved 0b r/w 2 reserved 0b r/w 1 0b: sdi2, input normal 1b: sdi2, input inverted 0b r/w 0 reserved 0b r/w control registers map and descriptions M08035, m08045 data sheet v1 macom ? 42 080x5-dsh-001 register address: 06h default: 20h register name: los config/clk en description: sets configuration for loss of signal al arm/enables serial clock output buffer register address: 07h default: 40h register name: input mux control description: selects the input that is selected for the serial data output bit bit description default r/w 7:5 000b: 70 mv ppd assert, 80 mv ppd de-assert 001b: 80 mv ppd assert, 90 mv ppd de-assert [default] 010b: 90 mv ppd assert, 100 mv ppd de-assert 011b: 100 mv ppd assert, 110 mv ppd de-assert 100b: 110 mv ppd assert, 120 mv ppd de-assert 101b: 120 mv ppd assert, 130 mv ppd de-assert 110b: 130 mv ppd assert, 140 mv ppd de-assert 111b: los power down (globally applied for all input channels) 001b r/w 4 0b: normal los operation 1b: force los to asserted 0b r/w 3 0b: squelch input upon los assertion 1b: never squelch input upon los assertion 0b r/w 2 0b: squelch to logic high state 1b: squelch to logic low state 0b r/w 1 reserved 0b r/w 0 0b: serial clock output is disabled 1b: serial clock output is enabled ( output level c ontrolled by reg0bh[3:2]) 0b r/w bit bit description default r/w 7:2 reserved 010000b r/w 1:0 00b: select input 0 to sdo 01b: select input 1 to sdo 10b: select input 2 to sdo 11b: select input 3 to sdo 00b r/w control registers map and descriptions M08035, m08045 data sheet v1 macom ? 43 080x5-dsh-001 register address: 09h default: 88h register name: sdoa ctrl description: sets output level and de-emphasis for sdo0 register address: 0ah default: 00h register name: data output de-emphasis control description: sets output level and de-emphasis for sdob. register address: 0bh default: 08h register name: output control description: sdoa mute and sdob/sclk swing control. bit bit description default r/w 7:4 reserved 1000b r/w 3:2 00b: sdo powered down 01b: sdo output swing = 600 mv ppd 10b: sdo output swing = 800 mv ppd 11b: sdo output swing = 1200 mv ppd 10b r/w 1:0 00b: sdo de-emphasis off 01b: sdo de-emphasis = small 10b: sdo de-emphasis = medium 11b: sdo de-emphasis = large 00b r/w bit bit description default r/w 7:6 reserved 000b r/w 5:4 00b: sdob de-emphasis off 01b: sdob de-emphasis = small 10b: sdob de-emphasis = medium 11b: sdob de-emphasis = large 00b r/w 3:0 reserved 00b r/w bit bit description default r/w 7:5 reserved 000b r/w 4 0b: sdoa output in normal operation 1b: sdoa output muted 0b r/w 3:2 00b: sdob/sclk output powered down 01b: sdob/sclk output swing = 600 mv ppd 10b: sdob/sclk output swing = 800 mv ppd 11b: sdob/sclk output swing = 1200 mv ppd 10b r/w 1:0 reserved 00b r/w control registers map and descriptions M08035, m08045 data sheet v1 macom ? 44 080x5-dsh-001 register address: 0ch default: 02h register name: sdob control description: enable for second data output. register address: 0dh default: 00h register name: global control1 description: controls global configuration register address: 0eh default: 00h register name: interrupt control description: sets configuration for xalarm output pin bit bit description default r/w 7:3 reserved 00000b r/w 2 0b: sdob output disabled 1b: sdob output enabled 0b r/w 1:0 reserved 10b r/w bit bit description default r/w 7:4 reserved 0000b r/w 3 0b: inputs that are no t used are powered down 1b: all inputs are forced on 0b r/w 2 reserved 0b r/w 1 0b: input offset correct ion loop on (all inputs) 1b: input offset correcti on loop off (all inputs) 0b r/w 0 0b: normal operation 1b: global power down 0b r/w bit bit description default r/w 7:4 reserved 00000b r/w 3 0b: xalarm output is used in interrupt mode 1b: not supported 0b r/w 2:0 000b: xalarm pulse width = 140 ns 001b: xalarm pulse width = 180 ns 010b: xalarm pulse width = 200 ns 011b: xalarm pulse width = 300 ns 100b: xalarm pulse width = 450 ns 101b: xalarm pulse width = 800 ns 110b: xalarm pulse width = 1.5 s 111b: xalarm pulse width = 2.8 s measured with a 10 k pull up resistor. actual pulse width vari es with the value of the pull-up resistor. 000b r/w control registers map and descriptions M08035, m08045 data sheet v1 macom ? 45 080x5-dsh-001 register address: 0fh default: 00h register name: memory interface configuration control description: defines the number of slave rclk devi ces, controlled by quasi master/eeprom 5.1.2 reclocker configuration register address: 12h default: 00h register name: reclocker control 0 description: controls reclocker register address: 14h default: 00h register name: reclocker control 1 description: controls reclocker bit bit description default r/w 7:6 reserved 00b r/w 5:0 000000b: no slave rclks 000001b: 1 slave rclk 000010b: 2 slave rclks 000000b r/w bit bit description default r/w 7:4 reserved 0000b r/w 3:2 00b: ard enabled 01b: sd data rate selected for reclocker 10b: hd data rate selected for reclocker 11b: 3g data rate selected for reclocker (m08045) 00b r/w 1 0b: normal operation (reclocker not bypassed) 1b: reclocker bypassed 0b r/w 0 0b: normal operation 1b: reclocker powered down 0b r/w bit bit description default r/w 7:1 reserved 0000b r/w 0 0b: normal operation 1b: reclocker auto-byp ass feature disabled 0b r/w control registers map and descriptions M08035, m08045 data sheet v1 macom ? 46 080x5-dsh-001 register address: 16h default: 20h register name: reclocker bw control description: controls bandwidth of reclocker register address: 18h default: 00h register name: sd/xhd algorithm control description: controls sd/xhd output of reclocker 5.1.3 checksum for memory interface configuration register address: 1ah default: 55h register name: checksum description: checksum value to be added to sum of reg 00h to 19h contents 5.1.4 status/monitoring register address: 80h default: 00h register name: reset description: does master reset on device bit bit description default r/w 7 reserved 0b r/w 6:4 000b: reserved (do not use) 001b: 0.5 x nominal lbw 010b: 1 x nominal lbw 011b: 4 x nominal lbw 100b: 2 x nominal lbw 101b: 3 x nominal lbw 110b: 1.5 x nominal lbw 111b: 0.875 x nominal lbw 010b r/w 3:0 reserved 0000b r/w bit bit description default r/w 7:6 reserved 00b r/w 5 0b: sd/xhd output conforms to case 1, table 4-11 1b sd/xhd output conforms to case 2, table 4-11 0b r/w 4:0 reserved 00000b r/w bit bit description default r/w 7:0 checksum value 01010101b r/w bit bit description default r/w 7:0 00h: normal operation aah: master reset 00000000b r/w control registers map and descriptions M08035, m08045 data sheet v1 macom ? 47 080x5-dsh-001 register address: 81h default: 0bh register name: chip id description: chip identification number register address: 82h default: 04h register name: chip rev description: chip revision register address: 83h default: 00h register name: los status 0 description: inputs 0-1, set to a '1' when los asserted (single-event latc hed operation). proper status is obtained after clearing all latc hed alarms by using register 85h bit 0. register address: 84h default: 00h register name: los status 1 description: inputs 2-3, set to a '1' when los asserted (single-event latc hed operation). proper status is obtained after clearing all latc hed alarms by using register 85h bit 0. bit bit description default r/w 7:0 M08035/m08045 n/a r bit bit description default r/w 7:0 chip revision 00000100b r bit bit description default r/w 7:6 reserved 00b r 5 0b: sdi1, input present 1b: sdi1, los asserted 0b r 4:3 reserved 00b r 2 0b: sdi0, input present 1b: sdi0, los asserted 0b r 1:0 reserved 00b r bit bit description default r/w 7:6 reserved 00b r 5 0b: sdi3, input present 1b: sdi3, los asserted 0b r 4:2 reserved 000b r 1 0b: sdi2, input present 1b: sdi2, los asserted 0b r 0 reserved 0b r control registers map and descriptions M08035, m08045 data sheet v1 macom ? 48 080x5-dsh-001 register address: 85h default: 00h register name: alarm clear description: clears latched alarms. to prope rly clear all alarm bits, write ? 1 ? followed by a ? 0 ? to bit 0. register address: 87h default: 00h register name: checksum result description: shows the result of the checksum calculation register address: 88h default: 00h register name: reclocker status register description: reads status of the reclocker register address: 89h default: 00h register name: reclocker rate detect description: reads data rate for reclocker bit bit description default r/w 7:2 reserved 000000b r/w 1 0b: normal operation 1b: soft reset for reclocker (for master reset use reg 80h) 0b r/w 0 0b: normal operation 1b: clears all alarm bits in registers 83h, 84h and 88h 0b r/w bit bit description default r/w 7:0 checksum result 00000000b r/w bit bit description default r/w 7:6 reserved 00b r 5 0b: reference clock is present 1b: reference clock is not present 0b r 4 0b: pll locked 1b: pll unlocked 0b r 3:1 reserved xxxb r 0 0b: reclocker, locked 1b: reclocker, un-locked 0b r bit bit description default r/w 7:2 reserved xxxxxxb r 1:0 00b: reclocker: un-locked 01b: reclocker: sd data rate detected 10b: reclocker: hd data rate detected 11b: reclocker: 3g data rate detected (m08045) 00b r www.macomtech.com general information: 100 chelmsford street lowell, massachusetts 01851 phone: 978.656.2500 ? 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M08035, m08045 data sheet v1 macom ? 49 080x5-dsh-001 |
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